Electrically controlled very high value floating cmos resistor

ABSTRACT

The present invention provides a circuit arrangement to convert fixed, or grounded resistors, to floating resistors. In particular, the circuit arrangement provides for the coupling of active electrical resistance devices to provide a relatively high value electrical resistance between two non-grounded nodes of the circuit arrangement in the order of Giga-ohms. The invention further provides for the magnitude of the floating electrical resistance to be determined by the magnitude of electrical current supply thus providing a means to select the magnitude of the floating electrical resistance by selecting by selecting the magnitude of electrical current supply. The circuit arrangement requires relatively few active devices and consumes a relatively small amount of electrical power in operation. The floating resistor of the present invention may be used in applications where a relatively high value resistor consuming a relatively small area of silicon, exhibiting relatively good linearity and wide dynamic range are required. Applications for such a device include neural networks, image processing and vision systems.

FIELD OF THE INVENTION

[0001] This invention relates generally to a means of providing a highvalue floating resistor for integrated electrical circuits and a methodof producing such a high value floating resistor. More particularly, theinvention relates to a circuit arrangement that provides for coupling toa grounded resistance device such that the circuit arrangement presentsa high value resistance between two floating, or non-grounded, nodes ofthe circuit arrangement.

BACKGROUND TO THE INVENTION

[0002] The physical constraints of integrated circuits do not allow forthe inclusion of standard fixed resistors as used in non-integratedelectrical circuits. However, in various applications, the use ofresistors, or resistance devices, in an integrated circuit isbeneficial.

[0003] As a result, various techniques have been employed in order toprovide an electrical resistance device in an integrated circuit thatmay be manufactured during the process of manufacturing the integratedcircuit device.

[0004] Most commonly, poly silicon was used to provide an electricalresistance in integrated circuit arrangements. Whilst this technique isfeasible, poly silicon is limited in the range of electrical resistanceit can present to the order of 1 to 3 kΩ's whilst at the same timeconsuming a relatively large region of silicon associated withwidespread end resistance value.

[0005] Alternatively, active devices such as MOSFET devices have beenused in a particular arrangement such that they present an electricalresistance between two nodes. Use of these devices has enabled theprovision of electrical resistances in the order of 500 to 600 kΩ's.

[0006] Whilst the use of MOSFET devices resulted in a significantimprovement with respect to the range of electrical resistance thatcould be generated in an integrated circuit, the arrangement of thesedevices requires that one node of the resistance device be coupled toground, or the circuit substrate.

[0007] In various applications, there is a requirement for circuits withlarge time constants. As the ability to provide capacitive devices inintegrated circuits is limited, there is a requirement for larger valuesof electrical resistance to satisfy the time constant requirements.Additionally, there is also a need for a high value electricalresistance device that has floating terminals.

SUMMARY OF THE INVENTION

[0008] In one aspect, the present invention provides an arrangement ofintegrated circuit devices including two matched transistors each in adiode connected configuration operating in the saturation region, thearrangement providing for coupling the transistors to a free terminal ofat least one grounded resistor such that the circuit arrangementpresents an electrical resistance between two non-grounded nodes of thecircuit arrangement.

[0009] The circuit arrangement thus effectively converts the at leastone grounded resistor coupled to the transistors to a floatingresistance device wherein both terminals of the resistance device areavailable for use in an integrated circuit.

[0010] The grounded resistor may be of any type including a passiveresistor constructed from poly silicon. However, in a preferredembodiment, the grounded resistor is a transistor operating as an activeresistance device.

[0011] The magnitude of the electrical resistance presented between thetwo non-grounded nodes of the circuit arrangement is dependent upon themagnitude of the grounded electrical resistance coupled to thetransistors of the circuit arrangement. In one particular circuitarrangement, the electrical resistance presented between the twonon-grounded nodes of the circuit arrangement is equivalent toapproximately twice the grounded electrical resistance coupled to thetransistors. There may be any number of grounded resistors coupled tothe transistors in a cascade arrangement thus determining the magnitudeof the electrical resistance presented between the two non-groundednodes of the circuit arrangement.

[0012] In a particularly preferred embodiment, two grounded transistorsoperating as active electrical resistance devices are coupledrespectively each of the matched transistors of the circuit arrangement.In this embodiment, the transistors are MOSFET devices with their gateterminals coupled together to form a current mirror arrangement.

[0013] In this preferred form, the magnitude of the electricalresistance presented between the two non-grounded nodes of the circuitarrangement may be in the Giga-ohm range.

[0014] At times, the properties between the floating terminals andground may include parasitics.

[0015] As a result of the circuit arrangement including the two diodeconnected matched transistors, the electrical resistance presentedbetween the two non-grounded nodes of the circuit arrangement will bedependent upon the channel length modulation parameter, λ. As thechannel length modulation parameter is process dependent, the magnitudeof the electrical resistance presented between the two non-groundednodes of the circuit arrangement will also be process dependent.

[0016] The skilled person in the art will appreciate that the electricalresistance is dependent on the output conductance of the device and theuse of λ is by way of a preferred arrangement only.

[0017] Reliance of the magnitude of the electrical resistance presentedbetween the two non-grounded nodes of the circuit arrangement upon theprocess used to implement the integrated circuit is limiting.Accordingly, in a particularly preferred embodiment, the groundedresistors in the form of MOSFET devices with their gate terminalscoupled together also have their gate terminals coupled to a thirdMOSFET device in a diode connected configuration to form a currentmirror arrangement. The third MOSFET device is coupled to a currentsource and operable to supply an electrical current to the currentmirror arrangement thus determining the magnitude of the electricalresistance presented by the grounded electrical resistance devices. As aresult, in this particularly preferred embodiment, the magnitude of theelectrical current supplied to the current mirror arrangement determinesthe magnitude of the electrical resistance presented between the two nongrounded nodes of the circuit arrangement. Thus, it is possible tocompensate or tune for the effects of the circuit arrangementsdependence upon the channel length modulation for the particular processof manufacturing the integrated circuit by predetermining the electricalcurrent supplied to the current mirror arrangement of the groundedactive electrical resistance devices.

[0018] In another aspect, the present invention provides a method ofdetermining the electrical resistance between two non-grounded nodes ofan arrangement of integrated circuit devices including two matchedtransistors each in a diode connect configuration with each transistorcoupled respectively to a grounded active resistance device, the activeresistance devices forming a current mirror configuration with the gateterminal of each grounded active resistance device coupled to variableelectrical current source, the method including the steps of:

[0019] Calculating the electrical current to be supplied to the coupledgate terminals of the active grounded resistance devices to produce arequisite conductance for each of the grounded active resistance devicesaccording to the relationship:

g _(d) =λI _(d)/(1+λV _(ds))≈λI _(d)

[0020] where

I_(d)=1 μA and λ=1 mV ⁻¹

[0021] the circuit arrangement thus providing an electrical resistancebetween the two non-grounded nodes of approximately twice the electricalresistance presented by each of the grounded active or passiveresistance devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The invention is now described by way of example with referenceto the accompanying drawings in which:—

[0023]FIG. 1 details a circuit arrangement comprising two diodeconnected matched transistors;

[0024]FIG. 2 details an embodiment of a complete circuit arrangementincluding the two diode connected matched transistors of FIG. 1 coupledto two grounded passive resistors;

[0025]FIG. 3 is a graphical representation of the electrical resistancebetween terminals V_(x) and V_(y) of the circuit arrangement of FIG. 2,the graphical representation resulting from a simulation of theoperation of the circuit arrangement;

[0026]FIG. 4 is a graphical representation of the total harmonicdistortion (THD) of the circuit arrangement of FIG. 2 as a function ofthe input signal amplitude in peak to peak voltage;

[0027]FIG. 5 details an embodiment of a complete circuit arrangementincluding two diode connected matched transistors coupled to twogrounded MOSFET devices operating as active resistance devices;

[0028]FIG. 6 is a graphical representation of the electrical resistancebetween terminals V_(x) and V_(y) of the circuit arrangement of FIG. 5for electrical current in the range of 7.5 μA to 20 μA, the graphicalrepresentation resulting from a simulation of the operation of thecircuit arrangement;

[0029]FIG. 7 is a graphical representation of the electrical resistancebetween terminals V_(x) and V_(y) of the circuit arrangement of FIG. 5for electrical current in the range of 500 nA to 1 μA, the graphicalrepresentation resulting from a simulation of the operation of thecircuit arrangement;

[0030]FIG. 8 details a circuit arrangement of a low frequencydifferentiator; and

[0031]FIG. 9A,9B are graphical representations of the frequency responseof the circuit arrangement of FIG. 8 with the circuit arrangementincluding ideal resistors and active resistance devices respectively.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0032] The following detailed description of the invention refers to theaccompanying drawings. Although the description includes exemplaryembodiments, other embodiments are possible, and changes may be made tothe embodiments described without departing from the spirit and scope ofthe invention.

[0033] It has been recognised that resistors and transconductors have animportant role in a wide variety of applications such as signalprocessing and neural networks, which generally utilise analogue VLSIcircuits.

[0034] In the following description it is assumed that the source andthe back gate for the corresponding n and p type MOS transistor areconnected together, unless it is specifically indicated otherwise.

[0035] The circuit arrangement of a preferred embodiment of theinvention includes two diode connect matched transistors operating inthe saturation region.

[0036] With reference to FIG. 1, the circuit arrangement details twodiode connected matched transistors operating in their saturationregion. In the instance of FIG. 1, the V_(x) and V_(y) nodes andrepresent the floating resistor terminals with I_(in)=I_(out) being thecurrent passing through the circuit arrangement.

[0037] Considering the currents I1 and I2, an expression for each ofthese currents may be written as:

I₁ =K/2(V _(y) −V ₂ V _(T))²  (1)

I ₂ =K/2(V _(x) −V ₁ −V _(T))²  (2)

[0038] where

[0039] K=μ₀C_(ox) (W/L), A/V²

[0040] μ₀ is the carrier mobility, cm²/(V_(S))

[0041] C_(ox) is the oxide capacitance per unit area, F/m²;

[0042] V_(T) the MOS transistor threshold voltage, V;

[0043] The current passing through the circuit arrangement of FIG. 1 maybe expressed as:

I_(in) =I _(out) =I ₂ −I ₁  (3)

[0044] From equations (1), (2) and (3), I_(out) can be written as:

I _(out) =K/2[(V _(x) −V _(y))−(V₁ −V ₂)][(V _(x) +V _(y))−(V ₁ +V ₂)]−2V _(T)]  (4)

[0045] The equivalent resistance, R_(eqv) may be expressed as:

R _(eqv)=(V _(x) −V _(y))/I _(in)=(V _(x) −V _(y))/I _(out)  (5)

[0046] If we let

V ₁ =V _(x) −V _(T) +f(V _(x))  (6)

[0047] and

V ₂ =V _(y) −V _(T) +f(V _(y))  (7)

[0048] equation (4) can be written as:

I _(out) =K/2(f(V _(x))² −f(V _(y))²)  (8)

[0049] This last equation (8) shows that the current passing through thecircuit arrangement is independent of the MOS transistor thresholdvoltage and is a function of V_(x) and V_(y) and is proportional to K.

[0050] Circuit Arrangement Including Matched Transistors and IdealResistors

[0051] A complete circuit arrangement including two diode connectedmatched transistors operating in their saturation region is detailed inFIG. 2. The circuit arrangement of FIG. 2 satisfies equations 6 and 7.In this arrangement, the current passing through mn₁ is mirrored usingmn₂ and fed back to the V_(y) terminal of mn₃. In a similar manner, thecurrent passing through mn₃ is mirrored by mn₄ and fed back to the V_(x)terminal of mn₁. The circuit arrangement detailed in FIG. 2 includes twogrounded resistors, R, coupled to circuit nodes V₁ and V₂.

[0052] In the instance of FIG. 2, the two grounded resistors, R, areideal resistors for the purpose of analysis of the circuit arrangementincluding the two diode connected matched resistors operating in theirsaturation region.

[0053] The relationship between V₂ and V₁, while assuming an idealresistor connected between V₁ and ground, can be expressed as:

V ₁ =R(2I ₂)=KR(V _(x) −V ₁ −V _(T))²  (9)

[0054] Solving equation (9) for V₁ provides two solutions, the feasiblesolution being:

V ₁ =V _(x) −V _(T)+[(1−(1+2KR(V _(x) −V _(T)))^(1/2))/2KR]  (10)

[0055] A similar expression for V₂ can be expressed as:

V ₂ =V _(y) −V _(T)+[(1−(1+2KR(V _(y) −V _(T)))^(1/2))/2KR]  (11)

[0056] Comparing equations (10) and (11) with equations (6) and (7)respectively, f(V_(x)) and f(V_(y)) may be expressed as:

f(V _(x))=(1−(X)^(1/2))/2KR  (12)

f(V _(y))=(1−(Y)^(1/2))/2KR  (13)

[0057] where

[0058] X=1+2KR(V_(x)−V_(T))

Y=1+2KR(V_(y)−V_(T))

[0059] Substituting the values of f(V_(x)) and f(V_(y)) from equations(12) and (13) in equation (8), I_(out) may be written as:

I _(out)=(1/8KR ²)[(1−(X)^(1/2))²−[(1−(Y)^(1/2))²]  (14)

[0060] Assuming the square root of X>>1 and the square root of Y>>1,which is a valid assumption for large values of R, then equation (14)reduces to:

I _(out)=(1/8KR ²)(X−Y)  (15)

[0061] Substituting the values of X and Y in equation (15) with

V _(x) =V _(B) +V _(in)/2; and

V _(y) =V _(B) −V _(in)/2

[0062] equation (15) reduces to:

I _(out) =V _(in)/2R  (16)

[0063] Equation (16) illustrates that the equivalent floating resistorvalue is independent of the process model parameters and is alsoindependent of the MOS transistors threshold voltage. An expression forthe equivalent resistance R_(eqv) can be written by substitutingequation (16) into equation (5), resulting in the expression:

R _(eqv) =V _(in) /I _(out)=2R  (17)

[0064] Equation 17 shows that the voltage-current relationship of thecircuit arrangement of FIG. 2 resembles an ideal resistor with anequivalent electrical resistance equal to the sum of the groundedresistors, namely 2R.

[0065]FIG. 3 is a graphical representation of the electrical resistancebetween terminals V_(x) and V_(y) if the circuit arrangement of FIG. 2resulting from a simulation with all transistors sizes set toW/L=12μ/12μ using the HSPICE simulator with levels 3 and 13 modelparameters obtained from MOSIS (a US corporation providing the interfacebetween foundries and designers) for a 1.2μ double poly, double metal,n-well process. The simulation shows that the electrical resistancebetween terminals V_(x) and V_(y) is greater than the sum of the twogrounded resistors. This is due to the approximation made in equation(14). The introduced harmonic distortion by the circuit arrangement whenusing ideal resistors is detailed in FIG. 4.

[0066] With reference to FIG. 4, the total harmonic distortion (THD)introduced by the circuit arrangement is illustrated as a function ofthe peak to peak voltage input signal amplitude.

[0067] Circuit Arrangement Including Matched Transistors and ActiveResistance Devices

[0068] The analysis presented above remains valid if the ideal resistorsR are replaced by an active grounded resistor or conductance. Thecircuit arrangement can be used to convert a grounded active electricalresistance device to a floating resistance device by connecting twomatched grounded resistors or conductances at V₁ and V₂. As the circuitarrangement of FIG. 1 provides for the coupling of active electricalresistance devices, such as in the arrangement of FIG. 5, a very highvalue floating (VHVF) resistor can be presented between the terminalsV_(x) and V_(y). This is achieved in the preferred embodiment bycoupling a very high value active resistance device, or grounded outputconductance, between nodes V₁ and V₂ with the output conductance of theMOS transistor operating in the saturation region.

[0069] A MOS transistor biased with relatively small current provides avery high value output conductance in the range of Giga-ohms (GΩ's).However, a MOS transistor output conductance is dependent on the channellength modulation parameter λ, which is generally defined as:

λ=(ε_(si) /qN _(eff) V _(ds) −V _(Dsat))^(1/2) /L  (18)

[0070] Where

[0071] ε_(si) is the dielectric constant of silicon;

[0072] N_(eff) is the substrate doping density;

[0073] q is the electron charge;

[0074] V_(ds) is the drain to source voltage;

[0075] V_(Dsat) is the drain saturation voltage;

[0076] L is the drain saturation voltage;

[0077] From equation (18), it can be recognised by those skilled in theart that λ is a process dependent parameter. Generally, it is notconsidered desirable to produce a circuit arrangement the operation ofwhich relies upon a process dependent parameter. However, in theinstance of the circuit arrangement of the preferred embodiment, thedependence on the process dependent parameter λ can be compensated byadjusting the value of the current supplied by transistor mnn to thetransistors mn₅ and mn₆.

[0078] Using a simple transistor model which includes the channel lengtheffect, the output conductance gd of mn₅ or mn₆ may be calculated atconstant gate to source voltage as

g _(d) =λI _(d)/(1+λV _(ds))≈λI _(d)  (19)

[0079] where I_(d) is the drain current.

[0080] For an I_(d)=1 μA and λ=1 mV⁻¹ (extracted from level 13 modelammeters at 1 μA bias current), the equivalent floating resistor is 2GΩ.

[0081] The circuit shown in FIG. 5 was simulated using a large value ofreference current in the μA range, to demonstrate the circuit operationoutside the subthreshold region. The simulation result, with thereference current I_(o) was swept from 7.5 μA to 20 μA in 2.5 μA steps,the results of the simulation being detailed in FIG. 6.

[0082] The circuit arrangement detailed in FIG. 5 was re-simulated usinga small bias current in the nA range. This simulation was performed toensure that all transistors are operating in the subthreshold region ofoperation. The simulation results, with I_(s) sweeping from 500 nA to 1μA in 100 nA steps, are detailed in FIG. 7.

[0083] As can be seen from FIGS. 6 and 7, the circuit exhibits arelatively linear resistor characteristic in both regions of operation.

DESIGN EXAMPLE

[0084] To demonstrate the use of the high value resistor in a practicaldesign example, the circuit arrangement of the preferred embodiment wasused in the design of an active low frequency, current controlled, bandpass filter. This type of filter presents a major problem in motiondetection and biomedical systems including pacemakers.

[0085] The band pass filter requirements selected were:

[0086] (i). 100 Hz bandwidth;

[0087] (ii) the first cut-off frequency at 1 to 10 Hz with the second at100 Hz;

[0088] (iii) relatively high gain;

[0089] (iv) relatively small silicon area requirement with a capacitorof 1 pF; and

[0090] (v) moderate to low power consumption.

[0091] A band-pass filter with these requirements may be provided withthe circuit arrangement detailed in FIG. 8. A differentiator is used toset the lower cut-off frequency and an operational amplifier is used toprovide the required gain and to set the upper cut-off frequency, whichis function of the operational amplifier bias current.

[0092] The transfer function of the circuit detailed in FIG. 8 can beexpressed as:

H(s)=−A(s)(RCs)/(1+RCs)  (20)

[0093] where A(s) is the Amplifier gain.

[0094] The simulation results for the circuit detailed in FIG. 8 usingan ideal resistor, R, and the circuit arrangement of the preferredembodiment to provide a floating resistor are detailed in FIG. 9.

[0095] The upper and lower cut-off frequencies for the ideal andfloating resistor are slightly different due to the loading effect thefloating resistor causes to the filter which is not included in thefilter simulation with ideal resistors.

CONCLUSION

[0096] The present invention embodies many advantages including theprovision of a circuit arrangement to convert fixed, or groundedresistors, to floating resistors. In particular, the circuit arrangementof the present invention provides for the coupling of active electricalresistance devices to provide a relatively high value electricalresistance between two non-grounded nodes of the circuit arrangement inthe order of Giga-ohms.

[0097] A particularly preferred form of the invention provides for themagnitude of the floating electrical resistance to be determined by themagnitude of electrical current supply thus providing a means to selectthe magnitude of the floating electrical resistance by selecting themagnitude of electrical current supply

[0098] The circuit arrangement requires relatively few active devicesand consumes a relatively small amount of electrical power in operation.

[0099] The floating resistor of the present invention may be used inapplications where a relatively high value resistor consuming arelatively small area of silicon, exhibiting relatively good linearityand wide dynamic range are required. Applications for such a deviceinclude neural networks, image processing and vision systems.

[0100] Further advantages and improvements may very well be made to thepresent invention without deviating from its scope. Although theinvention has been shown and described in what is conceived to be themost practical and preferred embodiment, it is recognized thatdepartures may be made therefrom within the scope and spirit of theinvention, which is not to be limited to the details disclosed hereinbut is to be accorded the full scope of the claims so as to embrace anyand all equivalent devices and apparatus.

[0101] In any claims that follow and in the summary of the invention,except where the context requires otherwise due to express language ornecessary implication, the word “comprising” is used in the sense of“including”, i.e. the features specified may be associated with furtherfeatures in various embodiments of the invention.

1. An arrangement of integrated circuit devices including two matchedtransistors each in a diode connected configuration operating in thesaturation region, the arrangement providing for coupling thetransistors to a free terminal of at least one grounded resistor suchthat the circuit arrangement presents an electrical resistance betweentwo non-grounded nodes of the circuit arrangement.
 2. An arrangement asin claim 1 wherein said arrangement effectively converts the at leastone grounded resistor coupled to the transistors to a floatingresistance device wherein both terminals of the resistance device areavailable for use in an integrated circuit.
 3. An arrangement as inclaim 1 or claim 2 wherein the grounded resistor may be of any typeincluding a passive resistor constructed from poly silicon.
 4. Anarrangement as in any one of the above claims wherein said groundedresistor is a transistor operating as an active resistance device.
 5. Anarrangement as in any one of the above claims wherein the electricalresistance presented between the two non-grounded nodes of the circuitarrangement is equivalent to approximately twice the grounded electricalresistance coupled to the transistors.
 6. An arrangement as in claim 5wherein there are a plurality of grounded resistors coupled to thetransistors in a cascade arrangement thereby determining the magnitudeof the electrical resistance presented between the two non-groundednodes of the circuit arrangement.
 7. An arrangement as in claim 6wherein two grounded transistors operating as active electricalresistance devices are coupled respectively each of the matchedtransistors of the circuit arrangement the transistors being MOSFETdevices with their gate terminals coupled together to form a currentmirror arrangement.
 8. An arrangement as in any one of the above claimswherein the properties between the floating terminals and ground mayinclude parasitics.
 9. An arrangement as in any one of the above claimswherein the grounded resistors in the form of MOSFET devices with theirgate terminals coupled together also have their gate terminals coupledto a third MOSFET device in a diode connected configuration to form acurrent mirror arrangement.
 10. An arrangement as in claim 9 wherein thethird MOSFET device is coupled to a current source and operable tosupply an electrical current to the current mirror arrangement thusdetermining the magnitude of the electrical resistance presented by thegrounded electrical resistance devices.
 11. A method of determining theelectrical resistance between two non-grounded nodes of an arrangementof integrated circuit devices including two matched transistors each ina diode connect configuration with each transistor coupled respectivelyto a grounded active resistance device, the active resistance devicesforming a current mirror configuration with the gate terminal of eachgrounded active resistance device coupled to variable electrical currentsource, the method including the steps of: calculating the electricalcurrent to be supplied to the coupled gate terminals of the activegrounded resistance devices to produce a requisite conductance for eachof the grounded active resistance devices according to the relationship:g _(d) =λI _(d)/(1+λV _(ds))≈λI _(d) where I_(d)=1 μA and λ=1 mV ⁻¹ thecircuit arrangement thus providing an electrical resistance between thetwo non-grounded nodes of approximately twice the electrical resistancepresented by each of the grounded active or passive resistance devices.